1. Field of the Invention
The present invention relates to a polishing method and a method for fabricating a semiconductor device and, for example, relates to a polishing method of polishing a copper (Cu) film and a method for fabricating a semiconductor device, having such a polishing step.
2. Related Art
With increasing integration and higher performance of semiconductor integrated circuits (LSI) in recent years, new micro processing technologies have been developed. Particularly, there have been moves recently to change a wiring material from conventional aluminum (Al) alloys to copper (Cu) or Cu allows (hereinafter called Cu together) having lower resistance to make LSI operate faster. It is difficult to apply a dry etching method, which is frequently used for forming Al alloy wires, to Cu for micro processing. For this reason, a damascene method is mainly adopted for Cu, in which a Cu film is deposited on a dielectric film to which groove machining has been provided and then the Cu film is removed except that in portions where embedded in a groove by chemical-mechanical polishing (CMP) to form embedded wiring. After forming a thin seed layer by a sputtering method or the like, the Cu film is generally formed into a laminated film having a thickness of several hundred nanometers by electrolytic plating. Further, when multi-layer Cu wiring is formed, particularly a method of forming wiring called a dual damascene structure can also be used. In this method, a dielectric film is deposited on lower layer wiring and predetermined via holes and trenches (wiring groove) for upper layer wiring are formed. Then, Cu to be a wiring material is embedded in the via holes and trenches simultaneously, and further unnecessary Cu in the upper layer is removed by CMP for flattening to form embedded wiring.
Recently, the use of a low dielectric constant material film with low relative dielectric constant (low-k film) has also been examined as an interlayer dielectric film. That is, an attempt has been made to reduce parasitic capacitance between wires by using a low-k film whose relative dielectric constant k is, for example, 3.5 or lower instead of a silicon oxide (SiO2 film) whose relative dielectric constant k is about 4.2. Moreover, a barrier metal film of tantalum (Ta) or the like is generally formed between the Cu film and the low-k film to prevent diffusion of Cu to the low-k film. Then, unnecessary portions of such a barrier metal film are also removed by CMP for flattening. In addition, unnecessary portions of the SiO2 film are removed by CMP for flattening.
The CMP method is, as described above, a technology widely used in high-performance LSI, memory and the like. Here, slurry, which acts as a polishing liquid, makes up a very large proportion among costs relating a CMP method, and thus there is a growing demand for reduction in flow rate of slurry. However, simply reducing the flow rate of slurry causes various problems such as a reduced polishing rate, increased dishing, and abnormal polishing due to a rise in polishing temperature. Then, also in a re-polishing for cleaning step performed after polishing in which, instead of slurry, a cleaning liquid is used, similarly the cleaning liquid costs very dearly. Also for the cleaning liquid, simply reducing the flow rate thereof causes not only reduced cleaning capabilities as process performance, but also various problems such as corrosion of metal portions. Thus, there has been a problem that the flow rate cannot be reduced, though reduction in flow rate of chemical fluids such as the polishing liquid and cleaning liquid has been desired.
A method of amassing slurry in a polishing pad has been disclosed as a technology to reduce the flow rate of slurry (see published Unexamined Japanese Patent Application Nos. 9-57608 and 2005-123232, for example). However, these technologies have a complicated mechanism, and it is currently very difficult to achieve a cost increase or cost reduction in additional equipment and process performance simultaneously.